A 96 �� 64 Intelligent digital pixel array with extended binary stochastic arithmetic

Citation

• Hammadou, T., Nilson, M., Bermak, A., & Ogunbona, P. (2003). A 96 �� 64 Intelligent digital pixel array with extended binary stochastic arithmetic. In Proceedings - IEEE International Symposium on Circuits and Systems Vol. 4.

Scopus Eid

• 2-s2.0-0038757578

Web Of Science Accession Number

Volume

• 4

Issue

Place Of Publication

Abstract

• A chip architecture that integrates an optical sensor and a pixel level processing element based on binary stochastic arithmetic is proposed. The optical sensor is formed by an array of fully connected pixels, and each pixel contains a sensing element and a Pulse Frequency Modulator (PFM) converting the incident light to bit streams of identical pulses. The processing element is based on binary stochastic arithmetic to perform signal processing operations on the focal plane VLSI circuit. A 96 �� 64 CMOS image sensor is fabricated using 0.5��m CMOS technology and achieves 29 �� 29��m pixel size at 15% fill factor.

UOW Authors

•   Ogunbona, Philip

Publication Date

• 2003

Citation

• Hammadou, T., Nilson, M., Bermak, A., & Ogunbona, P. (2003). A 96 �� 64 Intelligent digital pixel array with extended binary stochastic arithmetic. In Proceedings - IEEE International Symposium on Circuits and Systems Vol. 4.

Scopus Eid

• 2-s2.0-0038757578

Web Of Science Accession Number

Volume

• 4

Issue

Place Of Publication