An architecture of a real-time motion detection and velocity estimation system which can easily be implemented into a VLSI chip is presented. The system consists of the following components: image acquisition, edge extraction, velocity estimation, control, and I/O. Among the five parts of the system, the edge extraction and the velocity estimation units are the most important stages. A one-dimensional cellular automata network which emulates a parallel-iterative algorithm called edge relaxation, is employed to detect and track edges, and remove noise from the input binary image. A region-based velocity estimation is carried out by a digital circuit consisting of few counters and registers, a divider and an adder. The architecture can be extended to perform real-time motion estimation for two-dimensional gray-level images.