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Mixed mode real-time VLSI implementation of a shunting inhibition cellular neural network

Conference Paper


Abstract


  • In this paper a real-time mixed analog-digital VLSI implementation of a Shunting Inhibition Cellular Neural Network (SICNN) is presented. Unlike the usual VLSI implementation of vision chips, this circuit is based on a mixed analog-digital technology where the processing is realized using current mode analog approach while the cellular neural network topology (size of the window and connectivity) is realized using a modified digital read-out circuit. A significant processing speed-up is achieved using this technique since the window-based processing of the SICNN is realized in analog-domain while reading the pixel using the modified digital read-out circuit. A prototype including a 58 × 58 pixels and the SICNN processor with a programmable user-defined window size of 3 × 3 or 5 × 5 has been designed. The circuit also includes an amplifier and a successive approximation Analogue-to-digital converter. The circuit has been designed using Alcatel CMOS 0.7 μm technology and occupies a silicon area of 11mm2.

Publication Date


  • 2000

Citation


  • Bermak, A., & Bouzerdoum, A. (2000). Mixed mode real-time VLSI implementation of a shunting inhibition cellular neural network. In IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation (pp. 715-723).

Scopus Eid


  • 2-s2.0-0034507522

Start Page


  • 715

End Page


  • 723

Abstract


  • In this paper a real-time mixed analog-digital VLSI implementation of a Shunting Inhibition Cellular Neural Network (SICNN) is presented. Unlike the usual VLSI implementation of vision chips, this circuit is based on a mixed analog-digital technology where the processing is realized using current mode analog approach while the cellular neural network topology (size of the window and connectivity) is realized using a modified digital read-out circuit. A significant processing speed-up is achieved using this technique since the window-based processing of the SICNN is realized in analog-domain while reading the pixel using the modified digital read-out circuit. A prototype including a 58 × 58 pixels and the SICNN processor with a programmable user-defined window size of 3 × 3 or 5 × 5 has been designed. The circuit also includes an amplifier and a successive approximation Analogue-to-digital converter. The circuit has been designed using Alcatel CMOS 0.7 μm technology and occupies a silicon area of 11mm2.

Publication Date


  • 2000

Citation


  • Bermak, A., & Bouzerdoum, A. (2000). Mixed mode real-time VLSI implementation of a shunting inhibition cellular neural network. In IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation (pp. 715-723).

Scopus Eid


  • 2-s2.0-0034507522

Start Page


  • 715

End Page


  • 723