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3D packaging technology for vision CMOS VLSI: Review and performance evaluation

Conference Paper


Abstract


  • In many applications, such as multimedia and on-chip camera, there is a need for the production of low power, low weight and low cost integrated circuits. Several CMOS vision chips have been proposed in the literature. Some limitations of conventional 2D architectures are discussed and a new 3D generation of vision chips is presented and reviewed in this paper. As a result of this analysis, some conclusions on the advantages and limitations of 2D vision chips and the feasibility of the 3D approach are explored.

Publication Date


  • 1999

Citation


  • Bermak, A., Bouzerdoum, A., & Eshraghian, K. (1999). 3D packaging technology for vision CMOS VLSI: Review and performance evaluation. In Proceedings of SPIE - The International Society for Optical Engineering Vol. 3891 (pp. 248-256).

Scopus Eid


  • 2-s2.0-0033316595

Start Page


  • 248

End Page


  • 256

Volume


  • 3891

Abstract


  • In many applications, such as multimedia and on-chip camera, there is a need for the production of low power, low weight and low cost integrated circuits. Several CMOS vision chips have been proposed in the literature. Some limitations of conventional 2D architectures are discussed and a new 3D generation of vision chips is presented and reviewed in this paper. As a result of this analysis, some conclusions on the advantages and limitations of 2D vision chips and the feasibility of the 3D approach are explored.

Publication Date


  • 1999

Citation


  • Bermak, A., Bouzerdoum, A., & Eshraghian, K. (1999). 3D packaging technology for vision CMOS VLSI: Review and performance evaluation. In Proceedings of SPIE - The International Society for Optical Engineering Vol. 3891 (pp. 248-256).

Scopus Eid


  • 2-s2.0-0033316595

Start Page


  • 248

End Page


  • 256

Volume


  • 3891