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High fill-factor native logarithmic pixel: Simulation, design and layout optimization

Conference Paper


Abstract


  • In this paper we investigate important issues in the design of the logarithmic CMOS pixel. In particular, much attention is paid to the optimization of pixel performance in terms of output gain, dynamic range, and fill-factor. In order to increase the gain-bandwidth product, we propose to use the native transistor as source follower. The performance of such a pixel is compared with that of conventional logarithmic pixels. It is shown that the native source follower yields a significant increase in the gain-bandwidth product. In addition, we propose a layout floor-planning strategy which allows us to achieve a 46% fill-factor. In order to compare the performance of the proposed pixel with the conventional NMOS and PMOS logarithmic pixels, a VLSI prototype has been realized using 0.7 ��m CMOS technology.

Publication Date


  • 2000

Citation


  • Bermak, A., Bouzerdoum, A., & Eshraghian, K. (2000). High fill-factor native logarithmic pixel: Simulation, design and layout optimization. In Proceedings - IEEE International Symposium on Circuits and Systems Vol. 5. doi:10.1109/ISCAS.2000.857422

Scopus Eid


  • 2-s2.0-0033702502

Volume


  • 5

Issue


Place Of Publication


Abstract


  • In this paper we investigate important issues in the design of the logarithmic CMOS pixel. In particular, much attention is paid to the optimization of pixel performance in terms of output gain, dynamic range, and fill-factor. In order to increase the gain-bandwidth product, we propose to use the native transistor as source follower. The performance of such a pixel is compared with that of conventional logarithmic pixels. It is shown that the native source follower yields a significant increase in the gain-bandwidth product. In addition, we propose a layout floor-planning strategy which allows us to achieve a 46% fill-factor. In order to compare the performance of the proposed pixel with the conventional NMOS and PMOS logarithmic pixels, a VLSI prototype has been realized using 0.7 ��m CMOS technology.

Publication Date


  • 2000

Citation


  • Bermak, A., Bouzerdoum, A., & Eshraghian, K. (2000). High fill-factor native logarithmic pixel: Simulation, design and layout optimization. In Proceedings - IEEE International Symposium on Circuits and Systems Vol. 5. doi:10.1109/ISCAS.2000.857422

Scopus Eid


  • 2-s2.0-0033702502

Volume


  • 5

Issue


Place Of Publication